1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, to an organic electroluminescent display device which is capable of preventing in-line shorts and dropping of a supply voltage by forming a common power supply layer as a face plate.
2. Description of Related Art
FIG. 1A illustrates the cross-sectional structure of a conventional organic electroluminescent display device. FIG. 1B illustrates the plan structure of a conventional organic electroluminescent display device. FIG. 1A illustrates the cross-sectional structure for one pixel region as a cross-sectional structure taken along the line I—I of FIG. 1B.
Referring to FIG. 1A, a transparent insulation substrate 10 is divided into a first region 11 in which a pixel electrode is formed and a second region 12 in which a thin film transistor (TFT) and a capacitor are formed. A buffer layer 15 is formed on the insulation substrate 10, and a thin film transistor and a capacitor are formed in the second region 12 at the upper part of the buffer layer 15.
The thin film transistor is formed on the buffer layer 15 and equipped with a semiconductor layer 20 having source/drain regions 21 and 22, a gate electrode 31 on a gate insulating layer 30 and source/drain electrodes 51 and 52 which are formed on an interlayer insulating layer 40 so as to be respectively connected to the source/drain regions 21 and 22 through contact holes 41 and 42. The capacitor comprises a first electrode 32 formed on the gate insulating layer 30 and a second electrode 53 formed on the interlayer insulating layer 40 so as to be connected to the source electrode 51. A part interposed between the first and second electrodes 32 and 53 of the capacitor in the interlayer insulating layer 40 functions as a dielectric layer of the capacitor.
On the other hand, an organic electroluminescent display device is formed in the first region 11. The organic electroluminescent display device is equipped with a first pixel electrode 70 which is formed on a passivation layer 60 so as to be connected to the drain electrode 52 through a via hole 61, an organic electroluminescent EL layer 90 formed on the first pixel electrode 70 in an opening part 81 and a second pixel electrode 95 which is formed on a planarization layer 80 comprising the organic EL layer 90.
Referring to FIG. 1B, the organic electroluminescent display device is equipped with a plurality of signal lines, i.e., gate lines 35 used in selecting pixels, data lines 55 impressing data signals and power supply lines 56 giving a reference voltage required in driving a thin film transistor to drive by impressing an equal common voltage to all pixels.
Pixels are respectively arranged per each pixel regions limited by the signal lines 35, 55 and 56, wherein each of the pixels comprises a plurality of thin film transistors connected to the signal lines, for example, two transistors, one capacitor and an organic electroluminescent display device.
In fabricating a conventional organic electroluminescent display device, a first electrode 32 of capacitor and gate lines 35 are formed when forming the gate electrode 31 while a second electrode 53 of the capacitor, data lines 55, and power supply lines 56 are formed when forming the source/drain electrodes 51, 52, wherein one of the source/drain electrodes, for example, a source electrode 51 and a second electrode 53 of a capacitor are formed by being connected to the power supply lines 56.
Since the signal lines should be formed so that each of two signal lines are electrically separated on a layer as described above, there have been problems in that an in-line short (59 in FIG. 1B) occurs between data lines 55 and power supply lines 56 which are respectively adjacently arranged by conductive particles generated during the processing, and line defects are generated accordingly.
Furthermore, it is impossible to form a power supply line as a face plate, and the signal lines should be formed by patterning the power supply line in a line shape since each of the different two signal lines must exist on a layer. Accordingly, voltage drops are generated depending on positions to which a common voltage is impressed resulting in voltage non-uniformity, and resistance is increased due to line shape patterning resulting in a drop in voltage.
On the other hand, there have been problems in that the foregoing in-line shorts and drops in voltage are generated since two signal lines exist on one layer even in the case that the gate lines and power supply lines are formed at the same time while data lines are separately formed.